On-Line Randomness Test For Restart Random Number Generators

ABSTRACT

An apparatus includes a first counter for counting successive bits representative of a logic 1, and a second counter for counting successive bits representative of a logic 0, wherein a first predetermined count on the first counter or a second predetermined count on the second counter indicates a randomness failure. A method for testing randomness performed by the apparatus is also included.

BACKGROUND

One type of random number generator uses a drifting oscillator, designedto have large phase jitter. If the oscillator output is sampled slowlyenough, the sample values will be effectively random. An appropriatesampling rate must be utilized. If the sampling rate is too fast, thesample values will be mostly determined by the ratio of the oscillatorfrequency and the sample rate. If this ratio is not simple, as forexample 2:1 or 3:5, the sample sequence will look random, but in fact itwill be pseudo-periodic (meaning that the sequence deviates from aperiodic one only in a few places, determined by the occasional aboveaverage noise levels in the circuit). Detecting this problem on-line,that is, with a simple circuit constantly analyzing the generated samplesequence, is difficult because a pseudo-period can be quite long, and solarge buffers are necessary.

To avoid the problem of hard to detect low entropy, restart mode randomnumber generators have been proposed. After each sample is taken fromthe output of the drifting oscillator, the oscillator is reset. Theoscillator is always restarted from the same initial conditions. Theresult is larger randomness, because the drifting oscillator is moresensitive to noise in its start-up phase. In addition, instead ofintroducing pseudo-periodicity, sampling too fast causes long sequencesof equal output bits to be generated.

Sampling too fast can result in mostly equal samples, because theaccumulated jitter is not large enough to cause uncertainties at thesampling point. On-line randomness tests for restart mode random numbergenerators (e.g., sampled drifting oscillators) have to detect longsequences of equal samples. Many currently used randomness tests (suchas autocorrelation tests, poker tests, etc.) reliably detect a possibleproblem of this kind, but these tests are unnecessarily complex andexpensive.

SUMMARY

In one aspect, the invention provides an apparatus including a firstcounter for counting successive bits representative of a logic 1, and asecond counter for counting successive bits representative of a logic 0,wherein a first predetermined count on the first counter or a secondpredetermined count on the second counter indicates a randomnessfailure.

In another aspect, the first counter is reset when a received bit is alogic 0, and the second counter is reset when a received bit is a logic1.

In another aspect, the invention provides a method including: receivinga sequence of bits representing a plurality of logic 1's and 0's, usinga first counter to count successive bits representative of a logic 1until a logic 0 is received, using a second counter to count the bitsrepresentative of a logic 0 until a logic 1 is received, and producing afailure indication when either the first counter reaches a firstpredetermined count or the second counter reaches a second predeterminedcount.

These and other features and advantages will be apparent from a readingof the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an apparatus that can be used inaccordance with one aspect of the invention.

FIG. 2 is a flow diagram that illustrates an aspect of the invention.

DETAILED DESCRIPTION OF THE INVENTION

In various aspects, this invention provides a method and apparatus fortesting the randomness of a series of bits, by detecting the most likelyerroneous, non-random behavior. In one example, the series of bits canbe provided by a restart mode random number generator.

FIG. 1 is a schematic diagram of an apparatus 10 that can be used topractice one aspect of the invention. A random number generator 12includes a drifting oscillator 14 that produces a square-wave signalwith random edge jitter 16 on line 18. This signal can be in the form ofvoltage pulses, wherein the magnitude of the pulses represents a logic 1or 0. Due to oscillator drift and jitter, the timing and duration of thepulses will not be uniform. The random number generator further includesa sampler 20. A clock signal on line 22, which can be produced by aclock 24, is used to control the times at which the sampler samples thepulses and to reset the oscillator. Since the series of pulses issubject to drift and jitter, the output of the sampler should be aseries of random bits 26 on line 28.

The random number generator can operate in a restart mode, wherein it isrestarted after each clock signal 22, and the oscillator is brought intoa known initial state and begins to generate a series of pulses. Due todrift and jitter, the timing of the pulses becomes uncertain and thepulses can be sampled to produce a random sequence of bits. Onetechnique for on-line testing of the randomness of restart mode randomnumber generators detects long sequences of equal samples. FIG. 1provides a simple and inexpensive device that can implement this testtechnique.

In FIG. 1, the output of the sampler on line 28 is connected to a firstcounter 30 and a second counter 32. Each of the counters includes a datainput D, a clock input C, a reset input R, and an overflow output O. Thecounters can also include a plurality of outputs 34 and 36 thatrepresent a cumulative total of bits received on the data input betweenresets. An AND gate 38 has an inverting input 40 connected to line 28and another input 42 connected to the clock signal. The output 44 of theAND gate is connected to the reset input of the first counter. When alogic 1 is received at the data input of counter 30, the count on theoutputs 34 is incremented by 1. When successive logic 1's are receivedat the data input, the output will be the total number of successive1's. When a logic 0 is received at the data input of counter 30, thecounter is reset, and the output 34 is reset to all 0's. When thesamples are random, the counter is frequently reset to 0. This way, itdoes not reach a high counter value. When the samples include a longseries of logic 1's, the counter 30 may reach its maximum count andproduce an overflow signal on line 46. This overflow signal represents afailure indication, which indicates that the sequence of bits on line 28does not meet a desired randomness criteria.

The second counter 32 performs a similar function, but is reset when thecurrent sample is a logic 1, effectively determining the length of thelast all 0 sequence of the samples. This function is achieved by placingan inverter 48 between line 28 and the data input of counter 32. An ANDgate 50 has an inverting input 52 connected to the inverter output andanother input 54 connected to the clock signal. The output 56 of the ANDgate 50 is connected to the reset input of the second counter.

When the samples include a long series of logic 0's, the counter 32 mayreach its maximum count and produce an overflow signal on line 58. Thisoverflow signal can be used to indicate that the sequence of bits online 28 does not meet a desired randomness criteria. The overflowsignals from the two counters can be combined in an OR gate 60 toproduce a failure indication signal on line 62. Based on the failureindication signal, a controller 64 can then take appropriate action,such as adjusting the parameters of the oscillator 16 using a signal online 65; or increasing the sampling time by controlling the clock with asignal on line 66 to allow for more uncertainty in the sample pulses.Alternatively, or in addition, the controller may provide a failuresignal to the user of the random number generator on line 68.

In the example of FIG. 1, the two counters are incremented each time abit is output from the random number generator. In this example, asample is taken at each clock pulse. Alternatively, the counters canalso be incremented faster or slower, or decremented with the same endeffect.

Counter 30 is reset to the 0 count value when the current sample is alogic 0. This way, it does not reach a high counter value when thesamples are random, that is, the counter gets restarted often from 0.Similarly, counter 32 is reset, when the current sample is a logic 1,effectively determining the length of the last all 0 sequence of thesamples. When decrementing counters are used, a reset function can beimplemented by loading predetermined limit values to the counters, andthe overflow outputs would be activated, when the corresponding currentcount value reaches 0. Other counter configurations can be used toachieve the same effects.

The example of FIG. 1 uses an overflow signal as a failure indicationsignal. In another example, the output count of the counters could bemonitored and the failure indication signal could issue when the countreaches some predetermined value or number. The test fails if thepredetermined number is reached. At this point an interrupt command canissue, notifying the controller that an unusual event occurred.

In one example, if 5-bit counters are used, an interrupt can be issuedwhen one of the counters reaches the maximum value (i.e., 31),indicating that 32 successive identical samples were encountered. Thiscan occur in a truly random sequence, but very rarely. Its probabilityis 2⁻³², or one in 4 billion sequences of length 32. Such an occurrenceis so infrequent that a practical system might discard the last 32 bitsand continue operation. Then if the test fails again within a shortperiod of time, the controller can conclude that the random numbergenerator is broken, or under attack, and halts the random numbergeneration, but other failure policies are possible as well.

FIG. 2 is a flow diagram that illustrates an aspect of the invention.FIG. 2 shows a method that begins by receiving a sequence of bitsrepresenting a plurality of logic 1's and 0's, as shown in block 70. Afirst counter is used to count the bits representative of a logic 1, anda second counter is used to count the bits representative of a logic 0,as shown in block 72. Block 73 shows that the first counter is reset (orrestarted) when the binary bit is a logic 0, and the second counter isreset (or restarted) when the binary bit is a logic 1. If either thefirst counter reaches a first predetermined count or the second counterreaches a second predetermined count, a failure indication is produced,as shown in block 74.

The implementations described above and other implementations are withinthe scope of the following claims.

1. A method for determining contaminant particles in an aqueouspaper-making pulp comprising a) providing a screen assembly comprising ascreen supported in a housing, said housing having first and secondzones separated by said screen, a first port in said housingcommunicating with said first zone, and a second port in said housingcommunicating with said second zone, b) feeding an aqueous paper-makingpulp containing contaminant particles tangentially into said first zonethrough said first port, thereby producing a separation of heavycontaminants from lightweight contaminants in said first zone, feedingpulp fibres and lightweight contaminants along a first flow pathadjacent said screen in said first zone, and feeding the pulp fibresthrough said screen to deliver a flow of a screened aqueous suspensionof pulp fibres from said first zone to said second zone while retainingthe heavy and lightweight contaminants present in said aqueous pulp, insaid first zone, c) withdrawing the screened suspension through saidsecond port from said second zone, d) discontinuing steps (b) and (c),feeding a rinse fluid into said first zone to entrain residual pulpfibres in said first zone, and flush them through said screen as aflushed fibre suspension and withdrawing the flushed fibre suspensionthrough said second port from said second zone, while retaining saidheavy and lightweight contaminants accumulated in said first zone, e)discontinuing step (d), feeding a flush fluid into said first zone toentrain contaminant particles accumulated in said first zone, andflowing said entrained particles out of said first zone through saidfirst port, and f) recovering the contaminant particles from said flushfluid.
 2. A method according to claim 1 including a step g) evaluatingthe recovered contaminant particles as a determination of contaminantparticles in said aqueous paper-making pulp.
 3. A method according toclaim 2 wherein said aqueous paper-making pulp in step (b) is acontinuous sample flow withdrawn online from a pulp flow in pulp orpaper-making, and including issuing an instruction as to said pulp flowor paper-making in response to said evaluating in (e).
 4. A methodaccording to claim 1 wherein said steps (b) and (c) are carried out on acontinuous basis with a continuous flow of said aqueous paper-makingpulp into said first zone and a continuous flow of screened suspensionout of said second zone for a period of 0.75 to 24 hours, whereaftersteps (d) and (e) are carried out sequentially for a period of less than5 minutes each.
 5. A method according to claim 1 wherein said housing iscylindrical.
 6. A method according to claim 5 wherein said screen is acylindrical screen and said second zone is disposed outwardly of thecylindrical screen, said cylindrical screen having a bore forming partof said first flow path, and subjecting said aqueous pulp in said boreto pressure pulsations effective to prevent pulp fibres from pluggingsaid screen.
 7. A method according to claim 6 wherein said bore of saidcylindrical screen has a narrow annular entry opening for said pulp insaid first flow path which prevents entry into said bore of largecontaminant particles in said pulp, while permitting passage of pulpfibres and small contaminant particles.
 8. A method according to claim 1wherein the feeding of rinse fluid in step (d) includes a radial feed ofthe rinse fluid into a base lower region of said bore and a feed throughsaid first outlet, in said first zone.
 9. A method according to claim 3wherein said steps (b) and (c) are carried out on a continuous basiswith a continuous flow of said aqueous paper-making pulp into said firstzone and a continuous flow of screened suspension out of said secondzone for a period of 0.75 to 24 hours, whereafter steps (d) and (e) arecarried out sequentially for a period of less than 5 minutes each.
 10. Amethod according to claim 9 wherein said housing is cylindrical.
 11. Amethod according to claim 10 wherein said screen is a cylindrical screenand said second zone is disposed outwardly of the cylindrical screen,said cylindrical screen having a bore forming part of said first flowpath, and subjecting said aqueous pulp in said bore to pressurepulsations effective to prevent pulp fibres from plugging said screen.12. A method according to claim 11 wherein said bore of said cylindricalscreen has a narrow annular entry opening for said pulp in said firstflow path which prevents entry into said bore of large contaminantparticles in said pulp, while permitting passage of pulp fibres andsmall contaminant particles.
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